1. Field of Invention
The present invention is related to semiconductor testing, and in particular to testing CMOS I/O drivers.
2. Description of Related Art
As the integration of semiconductor chips continues, smaller and smaller geometries have occurred with more and more I/O circuits included to reduce the number of chips needed to implement a function. With the onset of advancement in displays creating LCD screens and other methods of display, the need for testing the ability of the I/O drive circuits to perform a specified function is necessary to guarantee the quality of the drivers. Driver leakage current testing as well as drive current capability is crucial to guarantee a quality display to insure segment and common connections to a display create a quality image.
A paper title “Verification and Auto Test for LCD Driver/Controller”, Zhuo et al., Proceedings 5th International Conference on ASIC, October 2003, Vol.: 2, pp.: 1175-1178 is directed to two methods that fulfill the voltage measurements for all terminals of an LCD driver using several A/D converters. U.S. Pat. No. 6,774,656 (Baur, et al.) is directed to a self-test for leakage current of driver/receiver stages. U.S. Pat. No. 6,725,171 (Baur, et al.) is directed to a self-test structure with a split, asymmetric controlled driver output stage. U.S. Pat. No. 6,262,585 (Frodsham, et al.) is directed to an apparatus for I/O leakage self-test in an integrated circuit.
In FIG. 1A is shown a driver circuit 10 of prior art, which comprises a driver logic 11, a P-channel transistor M1 and an N-channel transistor M2. The drain of transistor M2 is connected to the drain of transistor M1, which is further, connected to a chip I/O pad. A bias voltage +V is connected to the P-channel transistor M1 and a bias voltage −V is connected to the source of the N-channel transistor M2. The driver logic 10 controls the gates of M1 and M2 to produce at the I/O pad an output voltage and current to necessary to drive an LCD display or other electronic equipment. Testing of the driver circuit 10 requires probing of the I/O pad with a tester while manipulating the driver logic 11 to produce the required test conditions.
In FIG. 1B is shown a driver circuit 15 of prior art, which comprises the driver logic 16 controlling the gates of a first P-channel transistor M1, a second P-channel transistor M3 and an N-channel transistor M2. The drains of transistors M1 and M3 are connected to the drain of transistor M2 and further connected to a chip I/O pad. Transistor M1 is biased with a voltage +V, transistor M2 is biased with a voltage −V and transistor M3 is biased with a voltage +Vm. Testing of the driver circuit 15 requires probing of the I/O pad with a tester while manipulating the driver logic 16 to produce the required test conditions.
The probing of the small I/O pads of an integrated circuit chip by a tester exposes the I/O pad to damage, which creates problems for electrically connecting the I/O pads to the next higher level of assembly. A design and method is required to eliminate this exposure and still provide a means for efficiently testing the quality of the I/O drivers including leakage and drive current.